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Low-power way-predicting cache using valid-bit pre-decision for parallel architectures

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2 Author(s)
Hsin-Chuan Chen ; Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan ; Jen-Shiun Chiang

Focusing on the way-predicting cache with sub-block placement, we propose a new cache scheme that uses the valid bits from data memory to pre-decide disabling the unnecessary tag-subarrays and data-subarrays. By valid-bit pre-decision, it significantly helps in improving the average energy saving of the conventional way-predicting cache without valid-bit pre-decision, especially for with large associativity and small sub-block size. Moreover, the proposed way-predicting cache can be applied to the parallel architecture systems to reduce the overall power consumption.

Published in:

Advanced Information Networking and Applications, 2005. AINA 2005. 19th International Conference on  (Volume:2 )

Date of Conference:

28-30 March 2005