High performance CMOS converter design in TSMC 0.18-/spl mu/m process

This paper demonstrates the low voltage operation of a double balanced Gilbert mixer fabricated in 0.18-/spl mu/m standard/bulk CMOS process. A tuned load was used to ensure the rail-to-rail swing and a source degeneration resistor was used to improve the linearity. As an upconverter, the mixer demonstrates 1.65 dB of conversion gain at an RF frequency of 1.9 GHz with an applied local oscillator power of -1.2 dBm. The noise figure of the designed mixer is 17.2 dB, and the third-order input-referred intercept point (IIP3) is 20.45 dBm.