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This paper is concerned with design and IC implementation of a time interleaved pipelined ADC augmented to provide analog error outputs. The ADC outputs are used in digital-analog hybrid coding which uses residual error voltage transmission along with digital codes in a pipelined system of special design. The fully differential design in standard 0.18 μm CMOS technology employs a 12 bit, 60 MS/s paralleled-pipelined flash ADC. Such a pipeline ADC is the best candidate for applications where digital bit stream and analog residue both can be derived for hybrid digital-analog coding. Time interleaving provides increased throughput and signals for implementing QAM when necessary. The ADC targeted for achieving a high precision RF sensor telemetry application dissipates 90 mW from a single 1.8 V supply. Special attention has been given to ensuring adequate linearity for this system.. The digital-analog baseband signals are time/frequency multiplexed when transmitted on the RF carrier. The signal is regenerated in the receiver by summing the outputs of the DAC in the digital channel and the analog signal as necessary.