By Topic

Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques [CMOS transistors]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
8 Author(s)
Ribes, G. ; STMicroelectronics, Crolles, France ; Bruyere, S. ; Roy, D. ; Muller, M.
more authors

A very efficient trapping has already been reported on transistors with Hf-based gate oxides. The authors have attributed these phenomena to the presence of electron traps at the HfO2/SiO2, interface or in the HfO2 bulk. More recent experimental results show that the trapping occurs in the bulk of the high-k dielectrics rather than at the high-k/SiO2 interface. In this work, we apply an improved pulsed gate voltage technique for the electrical analysis of the transient charge trapping and detrapping effects, and based on the observed trapping and detrapping kinetics, we develop a new approach in order to characterize the energy distribution of the responsible HfO2 traps.

Published in:

Integrated Reliability Workshop Final Report, 2004 IEEE International

Date of Conference:

18-21 Oct. 2004