By Topic

Study of stress-induced leakage current and charge loss of nonvolatile memory cell with 70 Å tunnel oxide using floating-gate integrator technique

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Bin Wang ; Technol. Dev., Impinj Inc., Seattle, WA, USA ; Chih-Hsin Wang ; Yanjun Ma ; Diorio, C.
more authors

Techniques for measuring very low tunneling currents are critical for studying gate dielectric properties in MOSFETs, especially charge-loss mechanisms in nonvolatile memory (NVM) devices. Being able to measure stress-induced leakage current (SILC) at the floating gate operating conditions can be used to accurately extract the retention lifetime of floating gate memories. In this work, we utilize a floating-gate integrator technique (capable of resolving currents as low as 3×10-22 A) to study the effect of SILC on the charge-retention of logic NVM cells with a 70 Å tunnel oxide, with up to 300 k endurance cycles. The relation between SILC and Vox is used to extrapolate the retention lifetime of the memory cell. A conservative estimate of over 10 years retention is found for logic NVM with 70 Å gate tunnel oxides.

Published in:

Integrated Reliability Workshop Final Report, 2004 IEEE International

Date of Conference:

18-21 Oct. 2004