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Modified reduced adder graph algorithm for multiplierless FIR filters

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3 Author(s)
F. Xu ; Centre for High Performance Embedded Syst., Nanyang Technol. Univ., Singapore ; C. -H. Chang ; C. -C. Jong

A modified reduced adder graph (MRAG) algorithm and its hybrid version are proposed for efficient digital filter implementation. Several improvements are made to exploit fully the efficient optimal part of the n-dimensional reduced adder graph (RAG-n) algorithm. Simulation results demonstrate that MRAG is capable of generating lower adder cost solutions.

Published in:

Electronics Letters  (Volume:41 ,  Issue: 6 )