Referenced Items are not available for this document.
A full adder is used to demonstrate a programming technique using binary functionality for increased functional density in quaternary look-up table-based field programmable gated arrays (FPGAs). The potential inefficiencies of using quaternary level functionality for these architectures are also illustrated.
Published in:
Electronics Letters
(Volume:41
,
Issue:
6
)
Date of Publication: 17 March 2005
- Page(s):
- 300 - 302
- ISSN :
- 0013-5194
- INSPEC Accession Number:
- 8404410
- Digital Object Identifier :
- 10.1049/el:20057762
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 18 April 2005
- Issue Date :
- 17 March 2005
- Sponsored by :
- Institution of Engineering and Technology
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