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A high-input-sensitivity decision D flip-flop integrated circuit was designed and fabricated in a self-aligned InP double heterojunction bipolar transistor technology (Ft=180 GHz, Fmax=220 GHz). Circuit measurements at 40 Gbit/s show excellent eye quality, 15-mV sensitivity, and good clock phase margin. Two optical experiments, i.e., assessment of decision circuit reamplifying, reshaping, and retiming capabilities in 40-Gbit/s nonreturn-to-zero (full rate) photoreceiver and 43-Gbit/s optical signal noise ratio measurement (21.8 dB/0.1 nm for 10-9 BER) are also presented.
Microwave Theory and Techniques, IEEE Transactions on (Volume:53 , Issue: 4 )
Date of Publication: April 2005