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An efficient systolic array implementation of the sign-LMS algorithm

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2 Author(s)
L. A. Viriato ; Bell Northern Res., Ottawa, Ont., Canada ; T. Aboulnasr

A bit-level systolic array of the implementation of the LMS algorithm is presented. The array is divided into a 2D convolver array and a linear updater array. The structure is 100% data flow efficient, requiring N/2 rows to implement N coefficients. The updater is made up of N/2 simple cells. The sign-LMS algorithm is used for updating the coefficients. All coefficients are updated every 2R clocks where R is the number of bits per coefficient and the clock is the bit-level clock (array clock)

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing  (Volume:39 ,  Issue: 5 )