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A novel parallel optical proximity correction (OPC) technique is proposed for process distortion compensation of layout mask in design and fabrication of very large scale integration (VLSI) circuits. Based on a genetic algorithm (GA), rule- and model-based correction methods, and domain decomposition algorithms, a parallel OPC system is successfully developed for the layout mask correction of VLSI circuits on a Linux-based PC cluster with the message passing interface (MPI) libraries. Tested on several layout patterns, the implemented pattern-based partition scheme shows good accuracy for the OPC-corrected layout mask of VLSI designs. Computational and parallel benchmarks, such as speedup and efficiency, are achieved and exhibit excellent performance of the developed system. Our approach provides an alternative in developing advanced computer aided design (CAD) tools and benefits design and fabrication of system-on-chip (SoC).