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This paper presents a compiler methodology for memory-aware mapping on 2-Dimensional coarse-grained reconfigurable architectures that aims in improving the mapped applications' performance. By exploiting data reuse opportunities, the methodology tries to overcome the data memory bandwidth bottleneck, which negatively influences the applications' performance. This is achieved by using foreground memory in the architecture and by properly placing operations in the processing elements. The methodology considers a realistic 2-Dimensional coarse-grained reconfigurable architecture template, which can model the majority of the existing coarse-grained architectures. The experimental results show that the execution time and memory accesses are reduced.
Date of Conference: 4-8 April 2005