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Application of binary translation to Java reconfigurable architectures

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2 Author(s)
Beck, A.C.S. ; Inst. de Informatica, Univ. Fed. do Rio Grande do Sul, Porto Alegre, Brazil ; Carro, L.

In this paper we present the impact of applying binary translation to a reconfigurable architecture able to execute Java bytecodes. Besides ensuring software compatibility and porting for different machines tracking technological evolutions, the dynamic transformation of any sequence of instructions in combinational logic allows for meaningful energy savings and is totally transparent for the software designer. Moreover, we can speed up even code without a high level of parallelism available, in order of 3.5 times on average, and up to 6.5 times, spending 14 times less energy, in average. We present first studies about the impact on power and area of this technique and compare our architecture with a couple of other Java architectures, including a VLIW one. Our work uses a coarse-grain array, ensuring fast reconfiguration and less control overhead.

Published in:

Parallel and Distributed Processing Symposium, 2005. Proceedings. 19th IEEE International

Date of Conference:

4-8 April 2005