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Exploiting Barriers to Optimize Power Consumption of CMPs

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4 Author(s)
C. Liu ; Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA ; A. Sivasubramaniam ; M. Kandemir ; M. J. Irwin

Power consumption is an important concern for future billion transistor designs. This paper proposes a novel technique for optimizing the power consumption of chip-multiprocessors (CMPs) using an integrated hardware-software mechanism. By using a high level synchronization construct, called the barrier, our technique tracks the idle times spent by a processor waiting for other processors to get to the same point in the program. Using this knowledge, the frequency of the processors can be modulated to reduce/eliminate these idle times, thus providing power savings without compromising on performance. Using real applications from the SpecOMP suite, and a complete system CMP simulator, we demonstrate that this approach can provide as much as 40% power savings (and 32% on the average across five applications) with little impact on performance.

Published in:

19th IEEE International Parallel and Distributed Processing Symposium

Date of Conference:

04-08 April 2005