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A systematic study of trade-offs in engineering a locally strained pMOSFET

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20 Author(s)
Nouri, F. ; Appl. Mater., Sunnyvale, CA, USA ; Verheyen, P. ; Washington, L. ; Moroz, V.
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We present the results of a study on the impact of process parameters on the performance of strain enhanced pMOSFETs with recessed SiGe S/D. Recess depth, channel length, layout sensitivity, and their subsequent impact on strain and hole mobility are explored. Micro-Raman spectroscopy (μRS), process simulations, device simulations, and electrical results are presented. A 30% improvement in drive current is demonstrated.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004