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8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology

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19 Author(s)
Jong-Ho Park ; Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea ; Sung-Hoi Hur ; Joon-Hee Leex ; Jin-Taek Park
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For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 μm2, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004

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