Referenced Items are not available for this document.
For the first time, 8 Gb multi-level cell (MLC) NAND flash memory with 63 nm design rule is developed for mass storage applications. Its unit cell size is 0.0164 μm2, the smallest ever reported. ArF lithography with off-axis illumination (OAI) was employed for critical layers. In addition, self-aligned floating poly-silicon gate (SAP), tungsten gate with an optimized re-oxidation process, oxide spacer and tungsten bit-line (BL) with low resistance were implemented.
Published in:
Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International
Date of Conference: 13-15 Dec. 2004
- Page(s):
- 873 - 876
- Print ISBN:
- 0-7803-8684-1
- INSPEC Accession Number:
- 8394503
- Digital Object Identifier :
- 10.1109/IEDM.2004.1419319
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
