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Design and process integration for high-density, high-speed, and low-power 6F2 cross point MRAM cell

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18 Author(s)
Asao, Y. ; Corporate R&D Center, Toshiba Corp., Kanagawa, Japan ; Amano, M. ; Aikawa, H. ; Ueda, T.
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A cross point (CP) cell with hierarchical bit line architecture was proposed for magnetoresistive random access memory (MRAM) based in Y. Shimizu et al. (2004). The new CP cell has a potential high density of 6F2 and a faster access time than the conventional CP cell. A cell layout design to realize 6F is proposed and associated issues are resolved. Further, a 1Mb MRAM chip based on this structure has been fabricated utilizing 0.13 μm CMOS technology and 0.24×0.48 μm2 magnetic tunnel junction (MTJ) sandwiched with the most efficient yoke wires ever reported. The access time of 250 ns and 1.5 V operations are successfully demonstrated with the integrated 1Mb chip.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004