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Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3 and thin AlN) and TaN/HfO2 gate stack

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8 Author(s)
Whang, S.J. ; Silicon Nano Device Lab., Dept. of Electr. & Comput. Eng., Singapore National University, Singapore ; Lee, S.J. ; Fei Gao ; Nan Wu
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Ge-MOS devices (EOT ∼7.5 Å, Jg ∼ 10-3 A/cm2) are fabricated on both n- & p-type Ge-substrates, using novel surface passivation and TaN/HfO2 gate stack. Results show that the plasma-PH3 treatment and thin AlN layer at HfO2/Ge interface are effective to suppress the GeO formation, which is mainly formed during HfO2 deposition, and prevent Ge out-diffusion, resulting in improved C-V characteristics for n-MOS device with extremely low leakage. Thermal stability study of TaN/HfO2/Ge gate stack shows that low leakage with thin EOT can be obtained after post-anneal at 500 °C and degradation is observed above 600 °C. It is also observed that good Ge n+-p and p--n diode characteristics are achieved by S/D activation at 500 °C and 400°C, respectively. Both p- & n-MOSFETs are fabricated by conventional self aligned process with maximum temperature of 500 °C. Compared to reported Si-MOSFETs, the mobility enhancement of 1.6X for hole and 1.8X for electron is observed with Ge-MOSFETs.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004