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This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314μm2 build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.