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Aggressively scaled (0.143 μm2) 6T-SRAM cell for the 32 nm node and beyond

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31 Author(s)
Fried, D.M. ; Syst. & Technol. Group, IBM Semicond. R&D Center, Hopewell Junction, NY, USA ; Hergenrother, J.M. ; Topol, A.W. ; Chang, L.
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A 0.143 μm2 6T-SRAM cell has been fabricated using a planar SOI technology with mixed electron-beam and optical lithography. This is the smallest functional 6T-SRAM cell ever reported - consistent with cell areas beyond the 32 nm technology node. Enabling process features include a 25 nm SOI layer, shallow trench isolation (STI), 45 nm physical gates with ultra-narrow 15 nm spacers, novel extremely thin cobalt disilicide, 50 nm tungsten plug contacts, and damascene copper interconnects. Device threshold voltages (VT) and cell beta ratio (β) are optimized for cell stability at these aggressive ground rules. The 0.143 μm2 6T-SRAM cell exhibits a static noise margin (SNM) of 148 mV at VDD=1.0 V.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004