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Highly scalable sub-50nm vertical double gate trench DRAM cell

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14 Author(s)
Schloesser, T. ; Memory Dev. Center, Infineon Technol., Dresden, Germany ; Manger, D. ; Weis, R. ; Slesazeck, S.
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Results of a highly scalable 8F2 DRAM cell are presented. For the first time the fabrication of a fully depicted vertical transistor DRAM is demonstrated. Based on extensive process and device simulations, the scalability of the proposed cell beyond the 50nm DRAM node is highlighted.

Published in:

Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International

Date of Conference:

13-15 Dec. 2004

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