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Multiplier-less based parallel-pipelined FFT architectures for wireless communication applications

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4 Author(s)
Wei Han ; Sch. of Eng. & Electron., Edinburgh Univ., UK ; Arslan, T. ; Erdogan, A.T. ; Hasan, M.

This paper proposes two novel parallel-pipelined FFT architectures, based on multiplier-less implementation, targeting wireless communication applications, such as IEEE 802.11 wireless baseband chip and MC-CDMA receiver. The proposed parallel-pipelined architectures have the advantages of high throughput and high power efficiency. The multiplier-less architecture uses shift and addition operations to realize complex multiplications. By combining a new commutator architecture, and a low power butterfly with this approach, the resulting power and area savings are up to 31% and 20% respectively, for 64-point and 16-point FFTs, as compared to parallel-pipelined FFTs based on Booth coded Wallace tree multipliers.

Published in:

Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on  (Volume:5 )

Date of Conference:

18-23 March 2005

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