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A memory efficient serial LDPC decoder architecture

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2 Author(s)
Prabhakar, A. ; Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA ; Narayanan, K.

We present a memory efficient serial low density parity check (LDPC) decoder that implements a modified sum product algorithm (SPA). The modification is similar to the approximate min constraint presented by C. Jones et al. (see IEEE Conf. Military Commun., MILCOM 2003, p.157-162, 2003) but differs in hardware implementation to suit a serial architecture. Our main contribution is the proposed architecture that exploits the min constraint to reduce the storage of extrinsic messages which forms the bulk of the hardware. The least reliable bit to check input along with the check sum are the only quantities stored in the decoder. Extrinsic message memory reduction increases with the rate of the code and up to 68% saving is achieved for a rate 9/10 code. Simulation results show that the proposed changes do not degrade the bit error rate performance.

Published in:

Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on  (Volume:5 )

Date of Conference:

18-23 March 2005

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