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FPGA based implementation of decoder for array low-density parity-check codes

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3 Author(s)
Bhagawat, P. ; Texas A&M Univ., TX, USA ; Uppal, M. ; Gwan Choi

Low density parity check (LDPC) codes have received much attention for their excellent performance, and the inherent parallelism involved in decoding them. We consider a type of structured binary LDPC codes, known as array LDPC codes, which have low encoding complexity and good performance, for implementation on a Xilinx field programmable gate array (FPGA) device.

Published in:

Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on  (Volume:5 )

Date of Conference:

18-23 March 2005