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This paper addresses the design of a DFE for Gbits throughput rate in each communication path of a 10G base LX4 Ethernet system. It is well-known that the feedback loop within a DFE limits an upper bound of the achievable speed. For an L-tap feed-backward filter (FBF) with word-length W and M-PAM signal, previous authors have reformulated the FBF as a (log2M)L- to-1 multiplexer. However, the overhead of extra adders and extra multiplexers are as large as (log2M)L. The required hardware overhead would be more severe when the DFE is designed in parallel. In this paper, we propose two new approaches to implement the DFE when Gbit speed is required. The first approach is partial pre-computation, which can trade-off between hardware complexity and computation speed. The second approach is two-stage pre-computation, which can be applied to higher speed applications. We can reduce the hardware overhead to about 2(log2M)(-L2)/ times that of the previous authors, and the iteration bound is 2(log2W+2)/L+(log2M) multiplexer-delays.