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Integration of high-K dielectrics into sub-65 nm CMOS technology: requirements and challenges

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4 Author(s)
Misra, D. ; Dept. of Electr. Eng., New Jersey Inst. of Technol., Newark, NJ, USA ; Choudhury, N.A. ; Garg, R. ; Srinivasan, P.

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO2 and HfSiO2 will be focused.

Published in:

TENCON 2004. 2004 IEEE Region 10 Conference  (Volume:D )

Date of Conference:

21-24 Nov. 2004