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Design of low power current-mode flash ADC

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3 Author(s)
Bhat, M.S. ; Centre for Electron. Design & Technol., Indian Inst. of Sci., Bangalore, India ; Rekha, S. ; Jamadagni, H.S.

The design of a high-speed current-mode CMOS flash analog-to-digital converter (ADC) is presented. For high-speed operation, current mirroring technique with current comparison architecture is used and its advantages and limitations are explained. The optimization procedure is aimed at minimizing static power consumption, and its impact on circuit performance is investigated. A maximum sampling speed of 80 Ms/sec is achieved at 78 mW power consumption. The ADC is designed using 0.7-μm CMOS technology.

Published in:

TENCON 2004. 2004 IEEE Region 10 Conference  (Volume:D )

Date of Conference:

21-24 Nov. 2004