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FPGA implementation of a subspace tracker based on a recursive unitary ESPRIT algorithm

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2 Author(s)
P. Boonyanant ; Nat. Electron. & Comput. Technol., Thailand ; S. Tan-a-ram

This paper presents an FPGA implementation of a subspace tracker. The proposed design exploits a low-complexity property of a fast recursive ESPRIT algorithm. In addition, by applying a unitary transform, the system can be formulated in terms of real-valued computations. The simulation and real-time implementation are given based on 2-million gate Virtex II FPGA from Xilinx.

Published in:

TENCON 2004. 2004 IEEE Region 10 Conference  (Volume:A )

Date of Conference:

21-24 Nov. 2004