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High-speed parallel CRC circuits in VLSI

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2 Author(s)
Pei, T.-B. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Zukowski, C.

The use of VLSI technology to speed up cyclic redundancy checking (CRC) circuits used for error detection in telecommunications systems is investigated. By generalizing the analysis of a parallel prototype, performance is estimated over a wide range of external constraints and design choices. It is shown that parallel architectures fall somewhat short of ideal speedups in practice, but they should still enable current CMOS technologies to go well beyond 1 Gb/s data rates

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Communications, IEEE Transactions on  (Volume:40 ,  Issue: 4 )