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This work presents VLSI architecture in HMM-based speech recognition for high-speed operation and its verification platform to test various tasks on recognition systems. The proposed architecture effectively utilizes independent computations on the HMM structure. It can reduce processing time and/or extend the word vocabulary considerably. We designed a complete recognizer, including speech analysis and noise robustness parts, and developed a FPGA platform and a computer-aided design tool that generates source codes and testing data. The recognizer provides 35.7 μs/word in response time for word recognition tasks on a 0.18 μm CMOS technology and the FPGA platform enables real-time recognition experiments under various conditions.
Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on (Volume:2 )
Date of Conference: 26-29 Oct. 2004