By Topic

Design of FFT processor with low power complex multiplier for OFDM-based high-speed wireless applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Min Jiang ; Sch. of Comput. Sci. & Electr. Eng., Peking Univ., Beijing, China ; Bing Yang ; Yiling Fu ; Anping Jiang
more authors

We introduce a fixed-point 16-bit 64-point FFT processor for OFDM-based wireless applications. The processor is based on decimation-in-time (DIT) radix-2 butterfly FFT algorithm. The canonical signed digit is used to implement constant complex multiplications with carry save add (CSA) tree for lower power and cost. The simulation shows the module can reach low cost/power and high speed for OFDM-based high-speed wireless applications.

Published in:

Communications and Information Technology, 2004. ISCIT 2004. IEEE International Symposium on  (Volume:2 )

Date of Conference:

26-29 Oct. 2004