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Bit-level systolic imlementation of 1D and 2D discrete wavelet transform [imlementation read as implementation]

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1 Author(s)
Nayak, S.S. ; Dept. of Phys., S.K.C.G. Coll., Orissa, India

The author presents a systolic array architecture for VLSI implementation of the one-dimensional discrete wavelet transform (DWT) which computes both high- and low-pass frequency coefficients in the same clock cycle. The architecture is simple, modular and cascadable for computation of one- or multidimensional DWTs. It needs 62% fewer registers than existing architecture, and the hardware utilisation of the proposed structure is very high. Two systolic architectures are presented for bit-level VLSI implementation of 1D and 2D DWT. Matrix transposition is avoided in the systolic architecture for bit-level VLSI implementation of 2D DWTs.

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:152 ,  Issue: 1 )

Date of Publication:

4 Feb. 2005

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