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A high speed fuzzy inference processor with dynamic analysis and scheduling capabilities

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2 Author(s)
Shih-Hsu Huang ; Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung-li, Taiwan ; Jian-Yuan Lai

The most obvious architectural solution for high-speed fuzzy inference is to exploit the temporal parallelism and spatial parallelism inherited in a fuzzy inference execution. However, the active rules in a fuzzy inference execution are often only a small part of the total rules. In this paper, we present a new architecture, which uses less hardware resources by discarding non-active rules in the earlier pipeline stage. Implementation data demonstrates that the proposed architecture achieves very good results in terms of the inference speed and the chip area.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:2 )

Date of Conference:

6-9 Dec. 2004