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A 10-bit 350-Msample/s Nyquist CMOS digital-to-analog converter (DAC) is proposed In this work. The segmented current steering architecture that comprises 6 MSB's unary cells and 4 LSB's binary-weighted cells is applied in this design. Cascaded switch structure is adopted in the current cell which increases the performance of the segmented DAC. The simulation results show that integral nonlinearity is better than +0.15 LSB and differential nonlinearity is between +0.1 LSB. SNDR better than 60 dB is simulated in the interval from dc to the Nyquist frequency. The power consumption of this DAC with a single 2.5 V supply is 36 mW for a near-Nyquist fundamental signal at a 350-MHz update rate.