By Topic

DTA: layout design tool for CMOS analog circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Yen-Tai Lai ; Dept. of Electr. Eng., National Cheng Kung Univ., Tainan ; Jiang, Yung-Chuan ; Chi-Chou Kao

Layout is an important step in analog IC design. This paper presents an automation design of analog circuit layout by matching of devices and reducing noise coupling to decrease noise sensitivity. We first avoid the mismatch of constructing devices. Then, all devices are placed according to the wire length and area constraints. Finally, an effective approach is proposed to reduce noise coupling in the routing step. We have implemented our design method in several CMOS analog circuits. It can be seen that the proposed method can generate good analog circuit layout with specified timing constraints

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

6-9 Dec. 2004