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Low-error carry-free fixed-width multipliers and their application to DCT/IDCT

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4 Author(s)
Tso-Bing Juang ; Dept. of Comput. Sci. & Eng., National Sun Yat-sen Univ., Kaohsiung, Taiwan ; Shen-Fu Hsiao ; Shiann-Rong Kuang ; Ming-Yu Tsai

In this paper, we propose a low-error fixed-width redundant multiplier design. The design is based on the statistical analysis of the value of the truncated partial products in binary signed-digit representation with modified Booth encoding. The overall truncation error is significantly reduced with negligible hardware overhead. Simulation on DCT/IDCT of images with 256 gray levels shows our proposed multiplication design has higher PSNR/SNR.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

6-9 Dec. 2004