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Efficient testing and design-for-testability schemes for multimedia cores: a case study on DCT circuits

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4 Author(s)
Ming-Der Shieh ; Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan ; Sheng-Chih Shen ; You-Chung Lin ; Kuen-Jong Lee

Efficient test generation methods and design-for-testability schemes are critical to ensure the quality of multimedia cores. By investigating the potential test problems existing in these cores, This work presents a series of efficient test methods to significantly reduce the test application time for these cores while obtaining 100% fault coverage. The test development procedure is demonstrated by employing a well-known 2-D discrete cosine transform (DCT) circuit that is implemented in the typical row-column decomposition method. The 100% fault coverage is first achieved by appropriately modifying the original design, including scan design insertion and some ad hoc revisions. We then apply the recently-developed input reduction method and the broadcasting scan method to overcome the deficiency of long test application time when inserting scan design into the circuits. With these two methods, the test application time can be reduced to 6.8% of those required by the single full scan designs, while only 7.9% area overhead is needed.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

6-9 Dec. 2004