By Topic

Design of reconfigurable array multipliers and multiplier-accumulators

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Chin-Long Wey ; Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan ; Jin-Fu Li

A reconfigurable structure allows us to provide a large number of resources that can be used in different ways by different applications. This work presents the design methodology of reconfigurable array multipliers. A 64-bit reconfigurable multiplier can execute one 64-bit, two 32-bit, four 16-bit, and eight 8-bit multiplications depending upon three control signals. The hardware overhead includes 192 two-input AND gates and 3 control signals. Comparing with the original 64-bit array multiplier which requires 4032 full adders and 4096 two-input AND gates, the hardware overhead is very small. With additional metal lines for interconnections, the hardware overhead will not increase the chip area. In other words, the high reconfigurability of the developed circuit is achieved with negligible hardware overhead and virtually no performance overhead. The reconfigurable structure continues to use the conventional array multiplier with minor changes. This study also presents the design methodology of reconfigurable multiplier-accumulators (A×B+C) for signal processing applications.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

6-9 Dec. 2004