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CMOS system LSI for processing IEEE 802.11B WLAN PHY signals through digital, analog baseband, and RF

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12 Author(s)
Tsujimoto, T. ; Fukuoka Lab. for Emerging & Enabling Technol. of SoC, Fukuoka Ind., Sci. & Technol. Found., Japan ; Kanaya, H. ; Nakashi, K. ; Okamoto, K.
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We study CMOS system LSI for radio communication implemented with low energy consumption (low power) and low cost as key device for mobile and ubiquitous computing. We designed the trial mixed-signal CMOS chip for 2.4GHz wireless LAN (IEEE 802.11b) in TSMC's 0.25μm CMOS technology. As distinctive feature, coplanar waveguide (CPW) is used to realize the matching circuits placed between radio frequency (RF) amplifiers, at less cost than former inductor and capacitance (LC) circuit on chip. The trial chip operates the main functions of the 802.11b standard physical layer (PHY); carrier modulation by direct conversion, gain control, direct sequence spreading spectrum (DSSS), differential phase shift keying (DPSK) modulation, complementary code keying (CCK) modulation, framing the physical layer convergence procedure (PLCP) protocol data units (PPDUs), and, those reverse operations. This paper reports the structure of the trial chip containing RF circuits, base band analog circuits, and digital circuits on the very single chip.

Published in:

Circuits and Systems, 2004. Proceedings. The 2004 IEEE Asia-Pacific Conference on  (Volume:1 )

Date of Conference:

6-9 Dec. 2004

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