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This work presents a new efficient and stable multi-level partitioning algorithm for VLSI circuit design. As the most previous multi-level partitioning algorithms force experimental constraints on the process of hierarchy construction, the stability of their performance goes down. We minimize the use of experimental constraints and propose a new method for constructing partition hierarchy. The proposed method clusters the cells with the connection status of the circuit. In addition, we indicate the weakness of previous algorithms where they used a uniform method for choice of cells during the improvement. To solve the problem, we propose a new IIP (iterative improvement partitioning) technique that selects the method to choose cells according to the improvement status. The experimental result on ACM/SIGDA benchmark circuits show improvement up to 2-56% in minimum cutsize over previous algorithm and our technique outperforms hMetis by 2-9% in minimum cutsize.