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VLSI architectural design tradeoffs for sliding-window log-MAP decoders

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5 Author(s)
Chien-Ming Wu ; Chip Implementation Center, Nat. Appl. Res. Labs., Hsinchu, Taiwan ; Ming-Der Shieh ; Chien-Hsing Wu ; Yin-Tsung Hwang
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Turbo codes have received tremendous attention and have commenced their practical applications due to their excellent error-correcting capability. Investigation of efficient iterative decoder realizations is of particular interest because the underlying soft-input soft-output decoding algorithms usually lead to highly complicated implementation. This paper describes the architectural design and analysis of sliding-window (SW) Log-MAP decoders in terms of a set of predetermined parameters. The derived mathematical representations can be applied to construct a variety of VLSI architectures for different applications. Based on our development, a SW-Log-MAP decoder complying with the specification of third-generation mobile radio systems is realized to demonstrate the performance tradeoffs among latency, average decoding rate, area/computation complexity, and memory power consumption. This paper thus provides useful and general information on practical implementation of SW-Log-MAP decoders.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 4 )

Date of Publication:

April 2005

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