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A synthesizable RTL design of asynchronous FIFO

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3 Author(s)
Xin Wang ; Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland ; Ahonen, T. ; Nurmi, J.

An asynchronous FIFO which avoids data movement in a micropipeline FIFO is presented and it has been implemented as a gate-level netlist. The presented asynchronous FIFO model is constructed by commonly used hardware-description language and synthesized using the conventional EDA tools and methods for synchronous design. The purpose of this work is to construct a reusable asynchronous FIFO design which suits the commonly used synchronous design tools and flow.

Published in:

System-on-Chip, 2004. Proceedings. 2004 International Symposium on

Date of Conference:

16-18 Nov. 2004