Skip to Main Content
Future systems on chip for wireless and multimedia applications will have a strong demand for interoperability and inexpensive hardware solutions. Extended functionality, advanced signal processing functions and even multi-mode or multi-standard capabilities are an important design goal. Configurable architectures, arithmetic hardware accelerators or so called application specific instruction processors (ASIPs) are bridging the gap between application derived hardwired logic and software programmed general purpose microprocessors. For wireless and software defined radio applications this work presents selected baseband processing and error correction solutions as, for example, a Galois-field-ASIP-based decoder, a channel-processor and a WCDMA-transceiver. The concept and the prototype of the units was designed and verified by bit-true MatLab and System C/C++ based high level design methods. After synthesis and translation to a VHDL architecture description the design was tested in real-time on a high density DSP/FPGA-prototyping unit (PASS - Programmable Array System Simulator).
Date of Conference: 16-18 Nov. 2004