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A system-level multiprocessor system-on-chip modeling framework

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2 Author(s)
K. Virk ; Informatics & Math. Modeling, Tech. Univ. Denmark, Lyngby, Denmark ; J. Madsen

We present a system-level modeling framework to model system-on-chips (SoC) consisting of heterogeneous multiprocessors and network-on-chip communication structures in order to enable the developers of today's SoC designs to take advantage of the flexibility and scalability of network-on-chip and rapidly explore high-level design alternatives to meet their system requirements. We present a modeling approach for developing high-level performance models for these SoC designs and outline how this system-level performance analysis capability can be integrated into an overall environment for efficient SoC design. We show how a hand-held multimedia terminal, consisting of JPEG, MP3 and GSM applications, can be modeled as a multiprocessor SoC in our framework.

Published in:

System-on-Chip, 2004. Proceedings. 2004 International Symposium on

Date of Conference:

16-18 Nov. 2004