By Topic

Obstacle-avoiding rectilinear minimum-delay Steiner tree construction towards IP-block-based SOC design

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Jingyu Xu ; Dept. of Comput. Sci. & Technol., Tsinghua Univ, Beijing, China ; Xianlong Hong ; Tong Jing ; Yang Yang

With system-on-chip design, IP blocks form routing obstacles that deteriorate global interconnect delay. In this paper we present a new approach for obstacle-avoiding rectilinear minimal delay Steiner tree (OARMDST) construction. We formalize the solving of minimum delay tree through the concept of an extended minimization function, and trade the objective into a top-down recursion, which wisely produces delay minimization from source to critical sinks. We analyze the topology generation with treatment of obstacles and exploit the connection flexibilities. To our knowledge, this is the first in-depth study of the OARMDST problem based on topological construction. Experimental results are given to demonstrate the efficiency of the algorithm.

Published in:

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Date of Conference:

21-23 March 2005