By Topic

Voltage scaling, wire sizing and repeater insertion design rules for wave-pipelined VLSI global interconnect circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
V. V. Deodhar ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; J. A. Davis

This paper illustrates a method to determine the optimal voltage, wire sizing and repeater insertion design rules for a global wire routing level that uses wave-pipelined interconnect circuits. In order to balance performance, power and area, a throughput-per-energy-area (TPEA) metric is introduced to guide the design of a global wire routing level to achieve maximum throughput (i.e. bit-rate) with optimal utilization of resources. A 180 nm technology case study for a memory bus channel that requires an aggregate throughput of 332.8 Gbit/s illustrates that the optimal TPEA combination of 1 V supply, 6 repeaters per centimeter, a metal thickness to width aspect ratio of 2.5 and metal pitch to width ratio of 3 gives 12 % reduction in dynamic power and over 60 % reduction in wire area as compared to a published interconnect circuit that uses low voltage differential signaling (LVDS).

Published in:

Sixth international symposium on quality electronic design (isqed'05)

Date of Conference:

21-23 March 2005