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Modeling within-die spatial correlation effects for process-design co-optimization

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6 Author(s)
Friedberg, P. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Yu Cao ; Cain, J. ; Wang, R.
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Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.

Published in:

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Date of Conference:

21-23 March 2005