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Impact of on-chip inductance on power distribution network design for nanometer scale integrated circuits

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3 Author(s)
Srivastava, N. ; Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA ; Xiaoning Qi ; Banerjee, K.

This work presents a compact methodology for power distribution network design in a nanometer scale VLSI chip using a noise-area tradeoff analysis which considers on-chip inductance effects. This methodology is used to quantitatively demonstrate the importance of considering on-chip power grid inductance, and how its impact scales with technology. While increasing power supply noise levels (which become worse with on-chip inductance) are expected to adversely impact the chip's power supply grid design, this work demonstrates that a power grid optimized with on-chip inductance considerations can lead to significant improvement in the wiring resource utilization.

Published in:

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Date of Conference:

21-23 March 2005