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This paper presents a methodology for circuit analysis and yield optimization, where the most important and interesting features are the different modules with a strong focus on circuit analysis and yield improvement of the designed integrated circuits. Moreover, the possibility to analyze and size mixed-signal circuit design by a high flexibility and interactive use of the implemented methods and algorithms has been successfully used by designers for an exhaustive analysis of all devices to understand the circuit limitations before silicon results. In this case, we mainly focus on the usage of WiCkeD, deeply integrated in the Cadence Analog Design Environment. The proposed approach leverages the integration of WCDI/WiCkeD Cadence/MunEDA tools inside the Opus Design Framework: WCDI to read and collect data from Cadence Analog Design Environment and WiCkeD for circuit analysis and optimization purposes. Furthermore, the possibility both to detect all the structural constraints (i.e. saturation condition) with feasibility analysis and to separate mismatch parameters from statistical ones to show to the user which transistor parameter pairs cause largest performance drop by the mismatch effect, allows us to check, step by step, circuit consistency and the performance behaviour over a parameter during designing phases. The possibility of exporting the Analog Design Environment data towards WiCkeD for the synthesis setup and, later on, after the yield optimization step, the ability of annotating design parameters back to the Cadence Design Framework II allowed us to formalize and verify a methodology for circuit analysis and yield improvement, whose functionality has been proven on nonvolatile memories (NVM) proprietary technologies. Two main topics are addressed in this paper: first we focus on the different WiCkeD analysis and optimization modules to show the main advantages of this methodology, where circuit analysis is no longer a "black box". Afterwards, we use WiCkeD to optimize a bandgap voltage reference to improve the yield, addressing designers to better understand the circuit weakness.
Date of Conference: 21-23 March 2005