Skip to Main Content
Increased buffer insertion along on-chip global lines and the increasing contribution of leakage power have resulted in buffer leakage emerging as one of the chief contributors to system leakage power. We present a novel power-gating scheme for repeaters on global bus lines that address the pressing problem of runtime leakage while simultaneously eliminating worst-case capacitive coupling between adjacent bus lines. We propose using a pulsed MTCMOS (multiple threshold CMOS) scheme that dynamically activates the bus system only when transmitting a signal. Additionally, a bus encoding scheme is used to eliminate worst-case coupling and thereby negate the power-gating and pulse generation performance penalty. We consider all sources of delay and leakage power, including that of the MTCMOS control circuitry. This technique can result in nearly a 30% reduction in total bus system power for low switching activities and up to 2.3 times reduction in standby mode leakage with no reactivation delay penalty.