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Controlled-load limited switch dynamic logic circuit

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5 Author(s)
J. Sivagnaname ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; H. C. Ngo ; K. J. Nowka ; R. K. Montoye
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Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Published in:

Sixth international symposium on quality electronic design (isqed'05)

Date of Conference:

21-23 March 2005