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Controlled-load limited switch dynamic logic circuit

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5 Author(s)
Sivagnaname, J. ; Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA ; Ngo, H.C. ; Nowka, K.J. ; Montoye, R.K.
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Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Published in:

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Date of Conference:

21-23 March 2005